Conventionally, various wiring technologies have been provided for the purpose of efficient wiring of various types of boards. In recent years, in view of an increased demand for a printed circuit board for high-speed signal use, there is demand for development of a technology to support wiring design of forming a bus consisting of plural signal lines (nets) and wiring the bus as a bundle of lines. Specifically, in computer aided design (CAD) for the printed circuit boards, a number of automatic wiring technologies have been provided that enable automatic wiring by specification of the bus.
Further, there is demand for designers to reduce costs in wiring works. As a measure for cost reduction, an approach of wiring the printed circuit board as a whole at high density to minimize the number of wiring layers is effective. Specifically, consideration is made of whether there is any obstacle or any interference with a path of another bus, etc., based on the number of the nets in each bus, a line breadth, and a gap value. It becomes important at which layer and at which location to establish an area minimally required for the wiring (wiring area), namely, processing of determining the appropriate wiring area.
For example, a technology has been provided of determining the wiring area focusing attention on the path and information of each net pre-established by a designer or a system with respect to the bus to be wired on the printed circuit board. This technology is further provided with a function of taking into consideration overlapping of the determined wiring area of an object bus and the wiring area of an adjacent bus when judging whether the determined wiring area is appropriate (see, e.g., Japanese Patent Laid-Open Publication No. 2006-11684).
In the case of the conventional technology described above, however, in such a printed circuit board that has densely-packed buses, the degree of congestion of the printed circuit board differs depending on the order of the bus in which the wiring is executed and the determined wiring area can possibly be inappropriate. Therefore, when the wiring of the object bus is actually executed using the wiring area determined by the technology described above, an unwired signal line (unwired net) can occur.
Generally, the degree of congestion on the printed circuit board differs depending on the situation of the wiring and elements arranged on the printed circuit board when the wiring is instructed. It has been difficult to determine the minimally required wiring area so as not to cause any unwired net to all nets belonging to the bus. There has been a problem in that after the wiring area has been determined, an occurrence of any unwired net at the time of actual wiring execution brings about reworking of the wiring area at the layout design, increasing design time and design load and resulting in increased costs.